The present invention relates to an improved circuit structure for reducing leakage current due to the subthreshold characteristic of a MOS transistor, a semiconductor integrated circuit in which the operating voltage is kept constant, and a technique effectively applied to a large-capacity DRAM (Dynamic Random Access Memory) having a storage capacity of, for example, 256 Mbit to 1 Gbit or more.
In the case of an extremely-integrated semiconductor integrated circuit such as a DRAM, the operating voltage is lowered to 2 to 2.5 V because elements are microminiaturized and the threshold voltage of a MOS transistor is lowered to 0.15 to 0.2 V (conventionally, approx. 0.4 V) for speed-up. However, the leakage current (subthreshold current) due to the subthreshold characteristic of a MOS transistor is a problem. The subthreshold current is a leakage current which flows when the gate voltage is equal to or lower than a threshold voltage and the surface is weakly inverted.
Reducing the threshold voltage is disclosed in Japanese Patent Laid-Open Nos. 8-138381/1996, 6-232348/1994, 6-203558/1994, 5-210976/1993, and 5-347550/1993.
The present inventor has studied the application of a circuit for reducing the subthreshold current (Subthreshold Current Reduction Circuit: hereafter referred to as a SCRC) of a DRAM.
In FIG. 16 showing an example of the SCRC previously studied by the present inventor, logic circuits Li to L4 represented by a CMOS inverter are objects whose subthreshold currents are to be reduced. The period for which the subthreshold current must be reduced is, e.g., the standby period for which the input signal IN inputted to the logic circuit Li is set to a low level (xe2x80x9cLxe2x80x9d). Thereby, to prevent the subthreshold current from being generated in MOS transistors Qn1, Qp2, Qn3, and Qp4 to be turned off in the standby state, sub-power supply lines SL1 and SL2 are provided in addition to a main power supply line ML1 to which a power supply voltage VDD is supplied and a main power supply line ML2 to which a ground voltage VSS is supplied, a switch SD is provided between the main power supply line ML1 and the sub-power supply line SL1, and a switch SS is provided between the main power supply line ML2 and the sub-power supply line SL2. The switches SD and SS are controlled to be turned off in the standby state. When the switches SD and SS are turned off, the potential of the sub-power supply line SL1 becomes lower than the power supply voltage VDD of the main power supply line ML1 and the potential of the sub-power supply line SL2 becomes higher than the ground voltage VSS of the main power supply line ML2. Thereby, a reverse bias is applied between the gate and source of each of the off MOS transistors Qn1, Qp2, Qn3, and Qp4 in the logic circuits Li to L4, and the subthreshold current is reduced.
As a result of studying the above SCRC, the present inventor has found the following problems. The first problem of the SCRC is voltage drop due to the wiring resistance of the power supply lines, particularly the sub-power supply lines. In the case of the SCRC, the number of power supply lines is doubled to 4. Therefore, it is unavoidable to reduce the width of each line from the aspect of the layout, and thereby the wiring resistance increases. When the potential of the sub-power supply line SL1 on the power supply voltage VDD side is lowered due to the wiring resistance, and the potential of the sub-power supply line SL2 on the ground voltage VSS side rises, the operating speed of a logic circuit is lowered in an operable state.
The second problem is the area occupied by the switches SS and SD. In the case of a MOS semiconductor integrated circuit, the switches SS and SD are actually realized by using MOS transistors. To prevent the operating speed of the logic gate from lowering, it is necessary to minimize the resistance while a switching MOS transistor is on. Thus, it is necessary to increase the channel width of the MOS transistor and thereby, the layout area is increased.
It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the voltage drop of a sub-power supply line for reducing the subthreshold current and, thereby, preventing the operating speed of the logic circuit from lowering.
It is another object of the present invention to provide a semiconductor integrated circuit capable of consuming less power in the wait state and realizing speed-up during the operating time.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and accompanying drawings.
The outline of a representative invention among the inventions disclosed in this application is briefly described below.
That is, a plurality of switching MOS transistors for selectively connecting a main power supply line to a sub-power supply wiring are dispersedly arranged on one main power supply line. It is possible to use the following mode for the layout of main power supply lines, sub-power supply lines, and switches. Firstly, a main power supply line is provided along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply line. A plurality of switching MOS transistors for selectively electrically connecting a sub-power supply line with the main power supply line are dispersedly arranged on the main power supply line.
Secondly, the sub-power supply lines are arranged on the region in X and Y directions so that they are intersected and connected to each other at intersections like a so-called mesh. In this-ease, the main power supply line is provided along one side or two adjacent sides of the region.
Thirdly, the switching MOS transistors for connecting the main power supply line to the sub-power supply lines are arranged in a region immediately below the main power supply line.
When dispersedly arranging the switching MOS transistors on the main power supply line as described above, it is possible to reduce the equivalent wiring resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place because the distance between the MOS logic circuit whose subthreshold current must be reduced and the nearest switching MOS transistor is shortened. When MOS logic circuits whose subthreshold currents must be reduced are dispersed in the rectangular region, by arranging sub-power supply lines in the short side direction of the rectangular region, it is possible to use sub-power supply lines having a length equal to or less than the short side length of the rectangular region and further reduce the resistance components of the sub-power supply lines. Moreover, by arranging sub-power supply lines like a mesh so that power is fed to them from two directions of the main power supply line along two adjacent sides of the rectangular region, the equivalent wiring resistance of the sub-power supply lines is further reduced.
When the equivalent wiring resistances of the sub-power supply lines are reduced, the voltage drop on the sub-power supply lines is reduced in the operable state of the MOS logic circuit. Therefore, even if the subthreshold current is reduced, it is possible to prevent the operating speed of the MOS logic circuit from lowering. Moreover, it is possible to further reduce the power consumption of a semiconductor integrated circuit in the wait state.
When the main power supply line comprises a first main power supply line to which a first power supply voltage having a relatively high level is applied and a second main power supply line to which a second power supply voltage having a relatively low level is applied, the sub-power supply line connected to the source of a p-channel MOS transistor to be kept off in the MOS logic circuit in the above operation stop state is connected to the first main power supply line through the switching MOS transistor. Moreover, the sub-power supply line connected to the source of an n-channel MOS transistor to be kept off in the MOS logic circuit in the operation stop state is connected to the second main power supply line through the switching MOS transistor. The conductivity of carriers of a p-channel MOS transistor is approximately ⅓ the conductivity of carriers of an n-channel MOS transistor. Therefore, in the case of a CMOS circuit, the channel width of a p-channel MOS transistor is set to a value three times larger than the channel width of an n-channel MOS transistor. Thereby, the subthreshold current is produced by a p-channel MOS transistor more frequently than by an n-channel MOS transistor. Thus, when it is impossible to take a measure to reduce the subthreshold current for both n- and p-channel MOS transistors, it is expedient to take a measure for at least the p-channel MOS transistor.
A memory such as a DRAM frequently uses a voltage obtained by boosting a power supply voltage as a word line selection level in general. A MOS transistor constituting a MOS logic circuit using a boosted voltage as the operating voltage frequently uses a threshold voltage equal to that of a MOS transistor included in another circuit in order to simplify the fabrication process though the former has a high operating power supply voltage compared to the MOS transistors included in the other circuits. This is equivalent to the fact that the threshold voltage of a MOS transistor using a boosted voltage as the operation power supply lowers relatively to the operation power supply. This leads to the tendency to increase the subthreshold current. A semiconductor integrated circuit of the present invention considering the above point includes a plurality of memory mats including a large number of memory cells in which a word line is connected to a selection terminal and arranged like an array; a word driver for selectively driving word lines regularly arranged between the memory mats arranged like an array; a plurality of MOS logic circuits for supplying a word-line driving voltage to the word drivers regularly arranged between the memory mats arranged like an array; X-direction sub-power supply lines and Y-direction sub-power supply lines connected to power supply terminals of the MOS logic circuits, arranged in X and Y directions, and having a connection point at each intersection position; a main power supply wiring provided in the arrangement direction of at least one of the X- and Y-direction sub-power supply lines; and a plurality of switching MOS transistors for individually connecting all or part of the sub-power supply lines selected out of the X- and Y-direction sub-power supply lines to the main power supply-line; in which the switching MOS transistors are kept off in the standby state of the MOS logic circuits and kept on in the operable state of the MOS logic circuits. A boosted voltage is supplied to the main power supply line. The operation stop state is designated correspondingly to, for example, the chip non-selected state.
When a boosted voltage is supplied to the main power supply line, a source is connected to the sub-power supply line, and, thus, it is possible to supply the boosted voltage to the well region of a p-channel MOS transistor in the MOS logic circuit. Thereby, the threshold voltage of the p-channel MOS transistor tends to be raised, and, also, the subthreshold current is reduced.
A selection signal is received by a group of word drivers from a common main word line, and the MOS logic circuit supplies the word line driving level of the sub-power supply line to the word drivers in accordance with a decoding signal for selecting one word driver out of the word drivers. Because the main word line is provided for each group of a plurality of word drivers, the intervals between main word lines are relatively wide, and the sub-power supply lines are provided between the main word lines. That is, the sub-power supply lines are formed in the same wiring layer as the main word lines. Thereby, the chip area is not increased even if the number of sub-power supply lines increases.